1. Field of the Invention
The present invention relates generally to a moving detection circuit and more particularly to a moving detection circuit for generating a moving detection signal which is utilized in a television receiver such as a so-called improved definition television receiver (IDTV) for providing an improved image quality by using movement-adaptive type scanning line interpolation or the like.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of a prior art television receiver.
Referring to FIG. 1, a video signal is applied to an input terminal 62 and is supplied to an analog-to-digital (A/D) converter 63, where it is converted to a digital video signal. The digital video signal is then fed to a Y/C separating circuit 64, in which it is separated to provide a luminance signal Y and a chrominance signal C.
The luminance signal Y from the Y/C separating circuit 64 is supplied to a scanning line interpolating circuit 65Y. The chrominance signal C from the Y/C separating circuit 64 is supplied to a chroma decoder 66, where it is decoded to provide a time-division signal R-Y/B-Y of red and blue color difference signals R-Y and B-Y. The time-division signal R-Y/B-Y from the chroma decoder 66 is supplied to a scanning line interpolating circuit 65C. The scanning line interpolating circuits 65Y and 65C generate main scanning line signals Ym and Rm-Ym/Bm-Ym in addition to the interpolating scanning line signals Yc and Rc-Yc/Bc-Yc simultaneously.
The luminance signal Y from the Y/C separating circuit 64 is supplied to a moving detection circuit 50. The moving detection signal from the moving detection circuit 50 is supplied to a coefficient generator 51. The amplifying value K of the multipliers in the scanning line interpolating circuits 65Y and 65C is generated by the coefficient generator 51, and the value K changes in response to the magnitude of the moving detection signal. For example, K = 0 for the still picture portion and the maximum value of K is 1 for the rapid moving picture portion.
The moving detection circuit 50 will be described more fully with reference to FIG. 2.
Referring to FIG. 2, the luminance signal Y from the Y/C separating circuit 64 (see FIG. 1) is supplied to a series circuit comprising field memories 401 and 402 each of which form a delay line. The delay time of the series circuit of the field memories 401 and 402 is one frame (263H +262H).
The input signal to the field memory 401 and the output signal from the field memory 402 are supplied to a subtracter 403, where they are subtracted from each other. The frame difference signal from the subtracter 403 is supplied to a low-pass filter 404, in which the high band noise component and the dot interference component thereof are removed. The thus processed signal from the low-pass filter 404 is supplied to an absolute value circuit 405 where it is converted to an absolute value. The output signal from the absolute value circuit 405 is the moving detection signal.
Japanese Laid-Open Pat. No. 55-8124 discloses the above technique in which the moving detection signal is detected from the frame difference signal.
The scanning line interpolation circuit 65Y is constructed, for example, as shown in FIG. 3.
Referring to FIG. 3, the luminance signal Y delivered from the Y/C separating circuit 64 (see FIG. 1) is supplied to a line memory 601 which forms a delay line which has a delay time of 1H (one horizontal line period). The input and output signals of the line memory 601 are supplied to an adder 602, where they are added and averaged. The output signal from the adder 602 is multiplied by K (K .ltoreq. 1) by a multiplier 603, and is then fed to an adder 604.
The luminance signal Y from the Y/C separating circuit 64 (FIG. 1) is also supplied to a field memory 605 which forms a delay line. The delay time of the field memory 605 is selected to be 263H. The output signal from the field memory 605 is multiplied by (1 - K) by a multiplier 606, and is then fed to the adder 604.
FIG. 4 shows a scanning line structure from a time-vertical surface standpoint. In FIG. 4, an open circle represents the scanning line of each field. Assuming that h is the above-mentioned input signal, that i is the output signal of the line memory 601 and that j is the output signal of the field memory 605, and these signals h to j are arranged to have a positional relationship such as shown in FIG. 4.
In the scanning line interpolating circuit 65Y, the output signal h + i of the adder 602 is an interpolating scanning line signal which represents the real moving picture portion, whereas the output signal j of the field memory 605 is the interpolating scanning line signal which represents the still picture portion. The adder 604 generates an output which is an interpolating scanning line signal Yc in which the interpolating scanning line signals of the real moving picture and of the still picture portion are added at a ratio corresponding to the amount of movement. The scanning line which is to be interpolated is located as shown by a broken line circle in FIG. 4.
The input signal h is directly utilized as the main scanning line signal Ym.
The scanning line interpolating circuit 65C is similarly constructed and is not described in detail.
Referring back to FIG. 1, the main scanning line signals Ym and Rm-Ym/Bm-Ym and the interpolating scanning line signals Yc and Rc-Yc/Bc-Yc from the scanning line interpolating circuits 65Y and 65C are supplied to timebase-compressing circuits 67Y and 67C, respectively. The timebase-compressing circuits 67Y and 67C time-compress each of the main scanning line signals Ym, Rm-Ym/Bm-Ym and the interpolating scanning line signals Yc, Rc-Yc/Bc-Yc by one half respectively, and the signals are sequentially generated. In this case, the timebase-compressing circuit 67C generates red and blue color difference signals separately.
The double-speed luminance signal and color difference signals from the timebase-compressing circuits 67Y and 67C are supplied to digital-to-analog (D/A) converters 68Y, 68R and 68B, in which they are converted to analog signals, respectively.
The double-speed luminance signal and color difference signals from the D/A converters 68Y, 68R and 68B are supplied to a matrix circuit 73. The double-speed red, green and blue signals R, G and B from the matrix circuit 73 are respectively supplied through amplifiers 74R, 74G and 74B to a color cathode ray tube (color CRT) 75, where a color video signal which has double the normal scanning lines is displayed on the screen of the color CRT 75 according to the non-interlaced scanning system.
The television receiver shown in the example of FIG. 1 is disclosed, for example, in NEC technical report Vol. 41, No. 3/1988.
The chrominance signal component has a phase-inverting relationship between the frames so that when the luminance signal y contains the dot interference component, the output signal of the subtracter 403 (FIG. 2) also contains the dot interference component.
In the moving detection circuit 50 shown in the example of FIG. 2, when the low-pass filter 404 is formed as a so-called COS filter which has a frequency response characteristic which becomes lower around, for example, 3.58 MHz (refer to a solid line curve a in FIG. 5), movement of relatively high frequency can be detected. There is, however, presented such a problem in that the dot interference component (chrominance signal component) contained in the output signal from the subtracter 403 cannot be effectively removed. When on the other hand the low-pass filter 404 is formed as a so-called COS.sup.2 filter which has a response characteristic which becomes lower around, for example, 3.58 MHz (refer to a broken line curve b in FIG. 5), the dot interference component can effectively be removed but the moving detection ability so as to detect movement of a relatively high frequency is deteriorated.
Further, in the moving detection circuit 50 shown in FIG. 2, the frame difference signal is used as the moving detection signal, and the moving detection is performed during a unit of a frame frequency (1/30 second). There is then a problem because a quick movement such as a field frequency (1/60 second) cannot be detected, which fact causes a detection error to occur. This will be described more fully with reference to FIGS. 6A to 6D and FIGS. 7A to 7D.
FIGS. 6A, 6B and 6C respectively illustrate examples of luminance signals Y of two-fields before, one field before and the present field when the moving speed is low. In this case, the subtracter 403 generates an output signal such as shown in FIG. 6D, which does not have a detection error.
FIGS. 7A, 7B and 7C respectively illustrate examples of luminance signal Y of two-fields before, one field before and the present field when the moving speed is high. In this case, the subtracter 403 generates an output signal such as shown in FIG. 7D of which a portion P is the still picture portion. Thus, the movement in the unit of the field frequency cannot be detected, which fact causes a detection error.
To prevent a detection error from being caused when the moving speed is high, it is proposed to detect the movement by utilizing three or more field memories. This inevitably increases the memory capacity. Further, it is also proposed that a time base filter or the like be connected to the stage succeeding the moving detection circuit so as to remove the detection error. This proposal, however, requires more field memories, which fact causes the circuit scale to be increased.